KANEKO, Mineo Professor, Director of Security and Networks Area
School of Information Science, Security and Networks Area
B.E., M.E. and Ph.D. from Tokyo Institute of Technology (1981,1983,1986) 東京工業大学
B.E., M.E. and Ph.D. from Tokyo Institute of Technology (1981,1983,1986) 東京工業大学
B.E., M.E. and Ph.D. from Tokyo Institute of Technology (1981,1983,1986) 東京工業大学
◆Professional Experience
: Research Associate (1986), Lecturer (1988), Associate Professor (1992) at the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
Control and systems engineering, Electronic devices and equipment
◆Research Keywords
Integrated circuits, Electronic circuits, Circuit theory, CAD, Optimization, Algorithm
◆Research Interests

My current research interests include circuit theory and computer-aided-design for VLSIs, fault tolerant VLSI parallel computing toward dependable ULSI/WSI and Analog/Digital signal processing with emphasis on VLSI implementation.
Circuit theory and CAD for VLSIs:
VLSI is a collection of a huge number of transistors and interconnections between them, and its design is to find one or some configurations which satisfy specifications in the functional behavior. Various kinds of performances associated with each configuration, such as area, speed, power and testability, are necessary also to be optimized. Hierarchical design is inevitably introduced to transform the problem to be computationally manageable. Hence, besides optimization algorithms, the design model for each abstract level, by which the final VLSI performance can be well estimated/controlled and at the same time the problem size can be reduced to be a manageable level, is also a key for successful CAD for VLSIs. An unified design model which covers from Boolean circuit level to transistor level and relevant optimization algorithms is one of the current topics. This approach aims to generate further optimized circuits than the previous approaches can achieve. High-level synthesis and S/H co-design are also included in our interests but they are discussed in the context of Fault tolerance or VLSI signal processing.
Fault tolerant VLSI computing:
Parallelism and pipelining together with the well structured multiple processing elements are promising solutions to various computation problems in the field. Fault-tolerance and dependability as well will become the important functions for WSI/VLSI systems. Multiple modular redundancy in mixed spatial-temporal space, algorithm based fault tolerance, reconfiguration and unified theory of these techniques are studied with emphasis on WSI/VLSI computation. We are also interested in High-level synthesis for application specified fault tolerant VLSI systems and related design theory and algorithms.
VLSI signal processing:
The evolution in VLSI technology allows various complicated and computationally intensive algorithms to be implemented on VLSI chip. Performance measures for such VLSI computation include function and performance of a computation algorithm itself, area(hardware cost), computation time, throughput rate, accuracy (finite word length effects), power, etc. We are trying to find solutions through an approach of the algorithm/software/hardware co-design. Modularity and regularity analysis of numerical computation algorithms, algorithm transformation and optimization and interaction between algorithm transformation and software/hardware co-design are the central interests of ours.


◆Published Papers
A Novel Framework for Procedural Construction of Parallel Prefix Adders.
Mineo Kaneko
IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, 1-5, 2019
Special Section on Design Methodologies for System on a Chip FOREWORD
Kaneko Mineo
Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing.
Takayuki Moto, Mineo Kaneko
IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, 1-5, 2018
Wire congestion aware high level synthesis flow with source code compiler.
Masato Tatsuoka, Mineo Kaneko
2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018, 101-104, 2018
Mineo Kaneko
IEICE Transactions, 101-A, 7, 1000-1001, 2018
A General Model of Timing Correction by Temperature Dependent Clock Skew (VLSI設計技術) -- (デザインガイア2017 : VLSI設計の新しい大地)
金子 峰雄
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 117, 273, 183-188, 2017
Effect on the Chip Area of Component Adjacency Constraint for Soft-Error Tolerant Datapaths
呉 政訓, 金子 峰雄
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 116, 478, 151-156, 2017
Optimization of Parallel Prefix Adder Using Simulated Annealing
本 敬之, 金子 峰雄
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 116, 478, 139-144, 2017
Optimum Temperature Dependent Timing Skew for Temperature Aware Design
曽我 慎, 金子 峰雄
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 116, 478, 91-96, 2017
MILP Approach to Skew-Aware High Level Synthesis
志村 甲斐, 金子 峰雄
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 116, 478, 97-102, 2017
培風館, 2010
◆Conference Activities & Talks
電気関係学会北陸支部連合大会, 2011
部品配置の一アプローチ: Sequence Pair とその展開
電子情報通信学会 回路とシステム研究会, 2010
電子情報通信学会 コンピュテーション研究会, 2008
電子情報通信学会 VLD研究会, 2002
Assignment--Driven Heuristic Scheduling Based on Sensitivity to Iteration Period for Datapath Synthesis
Design Gaia 2001, 2001

■Teaching Experience

Literacy in Information Security Management, Exercises on Graph Theory, Foundation of VLSI Design(E), Foundation of VLSI Design, System Optimization(E), Digital Logic and Computer Design, System Optimization, 情報セキュリティ運用リテラシー, 演習グラフ理論, 集積回路特論(E), 集積回路特論, システム最適化(E), 計算機構成とインタフェース, システム最適化

■Contributions to  Society

◆Academic Society Affiliations
電気電子学会(The Institute of Electrical and Electronics Engineers), 電子情報通信学会, The Association for Computing Machinery, Information Processing Society of Japan, The Institute of Electrical and Electronics Engineers

■Academic  Awards

・ 編集活動感謝状 , 電子情報通信学会 基礎・境界ソサイエティ , 2013
・ Best Paper Award , IEICE , 2012
・ IEEE APCCAS'94 Best Paper Award , 1994