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金子 峰雄 (KANEKO, Mineo)教授, セキュリティ・ネットワーク領域長
情報科学系, セキュリティ・ネットワーク領域

発表論文

147件
Two-Graph Approach to Temperature Dependent Skew Scheduling
Mineo Kaneko
Proceedings of International Symposium on Quality Electronic Design, 432-437, 2020
Robustness Test Method of Power Flow System Containing Controllable and Fluctuating Power Devices
Saher Javaid, Mineo Kaneko, Yasuo Tan
2019 IEEE PES Asia-Pacific Power and Energy Engineering Conference (APPEEC), -, 2019
Power Flow Management: Solvability Condition for a System with Controllable and Fluctuating Devices
Saher JAVAID, Mineo KANEKO, Yasuo TAN
2019 IEEE PES Asia-Pacific Power and Energy Engineering Conference (APPEEC), -, 2019
A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices
Saher Javaid, Mineo Kaneko, Yasuo Tan
2019 IEEE 8th Global Conference on Consumer Electronics (GCCE), -, 2019
Power Flow Management for Smart Grids: Considering Renewable Energy and Demand Uncertainty
Saher Javaid, Mineo Kaneko, Yasuo Tan
2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), -, 2019
A Novel Framework for Procedural Construction of Parallel Prefix Adders.
Mineo Kaneko
IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, 1-5, 2019
Special Section on Design Methodologies for System on a Chip FOREWORD
Kaneko Mineo
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E101A, 7, 1000-1001, 2018
Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing.
Takayuki Moto, Mineo Kaneko
IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, 1-5, 2018
Wire congestion aware high level synthesis flow with source code compiler.
Masato Tatsuoka, Mineo Kaneko
2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018, 101-104, 2018
A random access analog memory with master-slave structure for implementing hexadecimal logic
Renyuan Zhang, Mineo Kaneko
International System on Chip Conference, 2017-, 7-11, 2017
Special section on VLSI design and CAD algorithms
Mineo Kaneko
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100A, 12, 2740-, 2017
A feasibility study of master-slave flipflop design for hexadecimal logic
Renyuan Zhang, Mineo Kaneko
IEACon 2016 - 2016 IEEE Industrial Electronics and Applications Conference, 232-237, 2017
Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis
Junghoon Oh, Mineo Kaneko
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E100A, 7, 1506-1510, 2017
KKT-condition based study on DVFS for heterogeneous task set
Mineo Kaneko
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, 717-720, 2017
Margin Aware Timing Test and Tuning Algorithm for Post-Silicon Skew Tuning
2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 1244-1247, 2017
KKT-condition inspired solution of DVFS with limited number of voltage levels.
Mineo Kaneko
IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, 1-4, 2017
Foreword.
Mineo Kaneko
IEICE Transactions, 100-A, 12, 2740-, 2017
A 16-valued logic FPGA architecture employing analog memory circuit
Renyuan Zhang, Mineo Kaneko
Proceedings - IEEE International Symposium on Circuits and Systems, 2016-, 718-721, 2016
Area-efficient soft-error tolerant datapath synthesis based on speculative resource sharing
Junghoon Ohy, Mineo Kanekoy
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E99A, 7, 1311-1322, 2016
Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing
Junghoon Oh, Mineo Kaneko
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E99A, 7, -, 2016
Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components
Junghoon Oh, Mineo Kaneko
2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 595-600, 2016
A 16-Valued Logic FPGA Architecture Employing Analog Memory Circuit
Renyuan Zhang, Mineo Kaneko
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 718-721, 2016
Mixed Error Correction Scheme and Its Design Optimization for Soft-Error Tolerant Datapaths
Junghoon Oh, Mine Kaneko
2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 362-365, 2016
Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism
Renyuan Zhang, Mineo Kaneko
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 20, 4, 64:1-64:19-, 2015
Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis
Junghoon Oh, Mineo Kaneko
Proceedings - IEEE International Symposium on Circuits and Systems, 2015-, 49-52, 2015
A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism
Renyuan Zhang, Mineo Kaneko
Proceedings - IEEE International Symposium on Circuits and Systems, 2015-, 942-945, 2015
A novel framework for temperature dependence aware clock skew scheduling
Mineo Kaneko
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 20-22-, 367-372, 2015
Bitwidth-Aware Register Allocation and Binding for Clock Period Minimization
Keisuke Inoue, Mineo Kaneko
2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), -, 2015
A Feasibility Study of Quaternary FPGA Designs by Implementing Neuron-MOS Mechanism
Renyuan Zhang, Mineo Kaneko
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 942-945, 2015
Automated Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis
Junghoon Oh, Mineo Kaneko
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 49-52, 2015
An analog VLSI implementation of one-class support vector machine for multiclass classification of highly dimensional vectors
Renyuan Zhang, Mineo Kaneko, Tadashi Shibata
JAPANESE JOURNAL OF APPLIED PHYSICS, 53, 4, -, 2014
Constrained binding and scheduling of triplicated algorithm for fault tolerant datapath synthesis
Mineo Kaneko, Yutaka Tsuboishi
Proceedings - IEEE International Symposium on Circuits and Systems, 1448-1451, 2014
System Design and Analysis for Maximum Consuming Power Control in Smart House
Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim
Journal of Automation and Control Engineering, 2, 1, 43-48, 2014
Scheduling of PDE Setting and Timing Tests for Post-Silicon Skew Tuning with Timing Margin
Mineo Kaneko
GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI, 91-92, 2014
Priority Based Maximum Consuming Power Control in Smart Homes
Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim
2014 IEEE PES INNOVATIVE SMART GRID TECHNOLOGIES CONFERENCE (ISGT), 1-5, 2014
Constrained Binding and Scheduling of Triplicated Algorithm for Fault Tolerant Datapath Synthesis
Mineo Kaneko, Yutaka Tsuboishi
2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 1448-1451, 2014
An ILP-based Optimal Circuit Mapping Method for PLDs
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
PROCEEDINGS OF 2014 IEEE INTERNATIONAL PARALLEL & DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 251-256, 2014
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin [Extended abstract]
Mineo Kaneko
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 91-92, 2014
A Feasibility Study on Robust Programmable Delay Element Design based on Neuron-MOS Mechanism
Renyuan Zhang, Mineo Kanoke
GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI, 21-26, 2014
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches
Keisuke Inoue, Mineo Kaneko
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A, 8, 1712-1722, 2013
Dual-edge-triggered flip-flop-based high-level synthesis with programmable duty cycle
Keisuke Inoue, Mineo Kaneko
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E96-A, 12, 2689-2697, 2013
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths
Keisuke Inoue, Mineo Kaneko
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A, 12, 2330-2337, 2012
Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis
Keisuke Inoue, Mineo Kaneko
2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 631-634, 2012
Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis
Keisuke Inoue, Mineo Kaneko
2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 778-783, 2012
Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis
Keisuke Inoue, Mineo Kaneko
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 1664-1667, 2012
Post-Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests
Mineo Kaneko, Jian Li
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 125-128, 2012
Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning
Mineo Kaneko
2012 IEEE 30TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 460-465, 2012
An efficient approach for designing and minimizing reversible programmable logic arrays
Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. H. Hasan Babu
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 215-220, 2012
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis
Keisuke Inoue, Mineo Kaneko
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 79-82, 2012
Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range
Keisuke Inoue, Mineo Kaneko
2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 239-244, 2012
Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A, 12, 2563-2570, 2011
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A, 4, 1067-1081, 2011
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis
Keisuke Inoue, Mineo Kaneko
Proceedings - IEEE International Symposium on Circuits and Systems, 550-553, 2011
Operation scheduling considering time borrowing for high-performance latch-based circuits
Keisuke Inoue, Mineo Kaneko
2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011, 245-248, 2011
Variable-Duty-Cycle Scheduling in Double-Edge-Triggered Flip-Flap-Based High-Level Synthesis
Keisuke Inoue, Mineo Kaneko
2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 550-553, 2011
Early planning for RT-level delay insertion during clock skew-aware register binding
Keisuke Inoue, Mineo Kaneko
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, 154-159, 2011
A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling
Mineo Kaneko
2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 189-195, 2011
Variable-Duty-Cycle Scheduling in Double-Edge-Triggered Flip-Flap-Based High-Level Synthesis
Keisuke Inoue, Mineo Kaneko
2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 550-553, 2011
Ordered coloring-based resource binding for datapaths with improved skew-adjustability
Mineo Kaneko, Keisuke Inoue
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 307-312, 2011
Framework for latch-based high-level synthesis using minimum-delay compensation
Keisuke Inoue, Mineo Kaneko
IPSJ Transactions on System LSI Design Methodology, 4, 232-244, 2011
Minimizing Clocking Patterns of Adjustable Safe Clocking for Timing Variation-Aware Datapaths
Keisuke Inoue, Mineo Kaneko
53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 113-116, 2010
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths
Keisuke Inoue, Mineo Kaneko
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 111-114, 2010
A pseudo-Boolean technique for generating compact transition tests with all-output-propagation properties
Tsuyoshi Iwagaki, Mineo Kaneko
Proceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010, 293-296, 2010
Optimal Register Assignment with Minimum-Delay Compensation for Latch-Based Design
Keisuke Inoue, Mineo Kaneko
PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 887-890, 2010
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E92A, 4, 1096-1105, 2009
On the Derivation of a Minimum Test Set in High Quality Transition Testing
Tsuyoshi Iwagaki, Mineo Kaneko
LATW: 2009 10TH LATIN AMERICAN TEST WORKSHOP, 71-76, 2009
Optimal Stall Insertion with Timing Skew Adjustment for Tunable LSIs
Keisuke Inoue, Takayuki Obata, Yayumi Uehara, Mineo Kaneko
2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 1187-1190, 2009
Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis
Takayuki Obata, Mineo Kaneko
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 1521-1524, 2009
Safe Clocking for the Setup and Hold Timing Constraints in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 27-32, 2009
Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis
Takayuki Obata, Mineo Kaneko
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3585-3595, 2008
Novel register sharing in datapath for structural robustness against delay variation
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 4, 1044-1053, 2008
Concurrent skew and control step assignments in RT-level datapath synthesis
Takayuki Obata, Mineo Kaneko
Proceedings - IEEE International Symposium on Circuits and Systems, 2018-2021, 2008
Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Wagaki
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 97-100, 2008
Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Wagaki
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 97-100, 2008
Concurrent skew and control step assignments in RT-level datapath synthesis
Takayuki Obata, Mineo Kaneko
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2018-2021, 2008
Safe Clocking Register Assignment in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 120-127, 2008
Loop pipeline scheduling for assignment constrained iteration period minimization
Koji Ohashi, Mineo Kaneko
WSEAS Transactions on Circuits and Systems, 6, 389-396, 2007
Statistical analysis driven synthesis of application specific asynchronous systems
Koji Ohashi, Mineo Kaneko
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A, 3, 659-669, 2007
Efficient path delay test generation based on stuck-at test generation using checker circuitry
Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 418-423, 2007
Solution space reduction of sequence pairs using model placement
Yuuki Yano, Mineo Kaneko
2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 912-915, 2007
FINE-printhead for sub-picoliter droplet
Mineo Kaneko, Ken Tsuchii, Takumi Suzuki, Masahiko Kubota
NIP 23: 23RD INTERNATIONAL CONFERENCE ON DIGITAL PRINTING TECHNOLOGIES, TECHNICAL PROGRAM AND PROCEEDINGS/DIGITAL FABRICATION 2007, 302-304, 2007
Parallel Computation of Data Summation for Multiple Problem Spaces on Partitioned Optical Passive Stars Network
Khin Thida Latt, Mineo Kaneko, Yoichi Shinoda
PROCEEDINGS OF WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY, VOL 21, 21, 184-189, 2007
Efficient path delay test generation based on stuck-at test generation using checker circuitry
Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 418-+, 2007
Extended Register-Sharing in the Synthesis of Dual-Rail Two-Phase Asynchronous Datapath
Koji Ohashi, Mineo Kaneko
GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 481-484, 2007
Analysis and optimization of statistical performance for asynchronous datapaths
Koji Ohashi, Mineo Kaneko
WSEAS Transactions on Circuits and Systems, 5, 895-902, 2006
Special section on VLSI Design and CAD Algorithms
Hidetoshi Onodera, Makoto Ikeda, Tohru Ishihara, Tsuyoshi Isshiki, Koji Inoue, Kenichi Okada, Seiji Kajihara, Mineo Kaneko, Hiroshi Kawaguchi, Shinji Kimura, Morihiro Kuga, Atsushi Kurokawa, Takashi Sato, Toshiyuki Shibuya, Yoichi Shiraishi, Kazuyoshi Takagi, Atsushi Takahashi, Yoshinori Takeuchi, Nozomu Togawa, Hiroyuki Tomiyama, Yuichi Nakamura, Kiyoharu Hamaguchi, Yukiya Miura, Shin-Ichi Minato, Ryuichi Yamaguchi, Masaaki Yamada, Yasushi Yuminaka, Takayuki Watanabe, Masanori Hashimoto, Masayuki Miyazaki
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3377-, 2006
Statistical property and subclass structure of sequence triple code space for repeated placements
Mine Kaneko
IEEE MWSCAS'06: Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, Vol II, 2, 580-584, 2006
Minimal set of essential resource disjoint pairs for exploring feasible 3D schedules
Mineo Kaneko
2006 IEEE Asia Pacific Conference on Circuits and Systems, 335-338, 2006
Statistical schedule length analysis in asynchronous datapath synthesis
Koji Ohashi, Mineo Kaneko
Proceedings - IEEE International Symposium on Circuits and Systems, 700-703, 2005
Control signal skew scheduling in RT level datapath synthesis
Takayuki Obata, Mineo Kaneko
Midwest Symposium on Circuits and Systems, 2005, 1087-1090, 2005
Sequence triple: A finite solution space for repeated placement
Mineo Kaneko
Midwest Symposium on Circuits and Systems, 2005, 1446-1449, 2005
Statistical schedule length analysis in asynchronous datapath synthesis
K Ohashi, M Kaneko
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 700-703, 2005
Statistical analysis driven synthesis of asynchronous systems
K Ohashi, M Kaneko
2005 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Proceedings, 200-205, 2005
Assignment constrained scheduling under max/min logic/interconnect delays for placed datapath
M Kaneko, K Ohashi
PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2, 1, 545-548, 2004
Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism
M Kaneko, K Oshio
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, 645-648, 2003
Characterization and computation of Steiner routing based on Elmore's delay model
Satoshi Tayu, Mineo Kaneko
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E85-A, 2764-2774, 2002
Assignment-driven loop pipeline scheduling and its application to data-path synthesis
Toshiyuki Yorozuya, Koji Ohashi, Mineo Kaneko
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E85-A, 819-826, 2002
Heuristic assignment-driven scheduling for data-path synthesis
K Ohashi, M Kaneko
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS, 703-706, 2002
3D scheduling based on code space exploration for dynamically reconfigurable systems
M Kaneko, J Yokoyama, S Tayu
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 465-468, 2002
Two-dimensional placement method based on divide-and-replacement
Y Takashima, A Kaneko, S Sato, M Kaneko
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 341-346, 2002
Characterization and computation of steiner wiring based on Elmore's delay model
S Tayu, M Kaneko
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 335-340, 2002
Reliable data routing for spatial-temporal TMR multiprocessor systems
M. Kaneko
IEICE Transactions on Information and Systems, E84-D, 1790-1800, 2001
Extended dimensional threshold filtering-a bridge between FIR filter and median type filter
Mineo Kaneko, Yasuaki Maekawa
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, 2, 309-312, 2001
An efficient scheme based on EMPDC graph model in synthesizing fa ul t tolerant FIR filter
CS Park, M Kaneko
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V, 5, 253-256, 2000
Assignment-space exploration approach to testable data-path synthesis for minimizing partial scan registers
M Kaneko, Y Shimizu, S Tayu
2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 540-543, 2000
An approximation algorithm for multiprocessor scheduling of trees with communication delays
S Tayu, M Katsura, M Kaneko
I-SPAN 2000: INTERNATIONAL SYMPOSIUM ON PARALLEL ARCHITECTURES ALGORITHMS AND NETWORKS, PROCEEDINGS, 114-120, 2000
An efficient scheme based on EMPDC graph model in synthesizing fa ul t tolerant FIR filter
CS Park, M Kaneko
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V, 253-256, 2000
Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications
M Kaneko, Y Nishio, S Tayu
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II, 57-60, 2000
Assignment-space exploration approach to concurrent data-path/floorplan synthesis
K Oohashi, M Kaneko, S Tayu
2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 370-375, 2000
Checking scheme for ABFT systems based on modified PD graph under an error generation/propagation model
Choon Sik Park, Mineo Kaneko
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82-A, 1002-1007, 1999
Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power
M Kaneko
ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, 1, 262-265, 1999
New adaptive algorithms based on multi-band decomposition of the error signal
Fernando Gil, V. Resende, Paulo S.R. Diniz, Keiichi Tokuda, Mineo Kaneko, Akinori Nishihara
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 45, 5, 592-599, 1998
VLSI/PCB placement with obstacles based on sequence pair
H Murata, K Fujiyoshi, M Kaneko
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 17, 1, 60-68, 1998
Reconfiguration of folded torus PE networks for fault tolerant WSI implementations
M Kaneko
APCCAS '98 - IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 791-794, 1998
LMS-based algorithms with multi-band decomposition of the estimation error applied to system identification
Fernando Gil, V. Resende, Paulo S.R. Diniz, Keiichi Tokuda, Mineo Kaneko, Akinori Nishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E80-A, 1376-1382, 1997
Multi-band decomposition of the linear prediction error applied to adaptive AR spectral estimation
Fernando Gil, V. Resende, Keiichi Tokuda, Mineo Kaneko, Akinori Nishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E80-A, 365-372, 1997
Multi-band decomposition of the linear prediction error applied to the least-mean-square method with fixed and variable step-sizes
FGV Resende, K Tokuda, M Kaneko, A Nishihara
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV, 4, 2176-2179, 1997
VLSI/PCB placement with obstacles based on sequence-pair.
Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997, 26-31, 1997
Adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error with variable forgetting factors
FGV Resende, PSR Diniz, M Kaneko, A Nishihara
1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V, 2293-2296, 1997
A study of the number of tracks required for the reconfiguration of mesh-connected processor-element networks
M Kaneko, T Tsunokawa, T Hirota, M Onoda
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 79, 11, 97-112, 1996
An adaptive algorithm based on nonuniform resolution filter
Y Naito, K Tokuda, M Kaneko
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 79, 9, 54-66, 1996
Adaptive ar spectral estimation based on wavelet decomposition of the linear prediction error
Fernando Gil, V. Resende, Keiichi Tokuda, Mineo Kaneko
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E79-A, 665-673, 1996
Link sharing scheme for fault tolerant systolic arrays based on mixed spatial-temporal triple modular redundancy
M Kaneko, H Miyauchi, CS Park
APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96, 472-475, 1996
RLS algorithms for adaptive AR spectrum analysis based on multi-band decomposition of the linear prediction error
FGV Resende, K Tokuda, M Kaneko, A Nishihara
1996 IEEE TENCON - DIGITAL SIGNAL PROCESSING APPLICATIONS PROCEEDINGS, VOLS 1 AND 2, 2, 541-546, 1996
Image restoration based on estimation of fractal structure
T Hamano, K Tokuda, M Kaneko
1996 IEEE TENCON - DIGITAL SIGNAL PROCESSING APPLICATIONS PROCEEDINGS, VOLS 1 AND 2, 1, 311-316, 1996
Concurrent cell generation and mapping for CMOS logic circuits
M Kaneko, JL Tian
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997, 247-252, 1996
Systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy
Mineo Kaneko, Hiroyuki Miyauchi
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 829-836, 1995
AR spectral estimation based on multi-window analysis of the linear prediction error
Fernando Gil Resende, Keiichi Tokuda, Mineo Kaneko
Midwest Symposium on Circuits and Systems, 1, 119-122, 1995
FAULT-TOLERANT NONREGULAR DIGITAL SIGNAL-PROCESSING BASED ON COMPUTATION TREE BLOCK DECOMPOSITION
M KANEKO, H MIYAUCHI
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E77A, 9, 1535-1545, 1994
BOUNDARY SEARCH APPROACH TO PARAMETER DESIGN FOR ANALOG CIRCUITS
M KANEKO, Y FUJIKAWA
APCCAS '94 - 1994 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, CAS94-97, 276-281, 1994
ROUNDOFF NOISE MINIMIZATION FOR RECURSION SPECIFIED FULLY PIPELINING DIGITAL FILTERS
T HIRAKURA, M KANEKO
APCCAS '94 - 1994 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 225-230, 1994
OSCILLATION FAULT DIAGNOSIS FOR ANALOG CIRCUITS BASED ON BOUNDARY SEARCH WITH PERTURBATION MODEL
M KANEKO, K SAKAGUCHI
1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, 1, A93-A96, 1994
AR SPECTRUM ESTIMATION BASED ON WAVELET REPRESENTATION
FG RESENDE, K TOKUDA, M KANEKO
1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, 2, B625-B628, 1994
A DISTRIBUTED RECONFIGURATION CONTROLLER FOR LINEAR ARRAY HARVEST PROBLEM - HIERARCHICALLY QUASI-NORMALIZED NEURAL APPROACH
S SUTIKNO, M KANEKO, M ONODA
1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, 4, D67-D70, 1994
A NOVEL CAPACITOR PLACEMENT STRATEGY IN ASCCOT - AUTOMATIC LAYOUTER FOR SWITCHED-CAPACITOR CIRCUITS
M KANEKO, M MASUDA, T HAYASHI
1993 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : PROCEEDINGS, VOLS 1-4 ( ISCAS 93 ), 3, 2094-2097, 1993
An efficient method for making a fault dictionary for short‐circuit fault diagnosis of linear networks
Kazuhiro Sakaguchi, Mineo Kaneko
Electronics and Communications in Japan (Part III: Fundamental Electronic Science), 75, 11, 1-11, 1992
Fault diagnosis with short circuit for linear analog networks
Kazuhiro Sakaguchi, Mineo Kaneko
Proceedings - IEEE International Symposium on Circuits and Systems, 4, 2068-2071, 1991
LOGICAL FUNCTION AND DELAY TIME EXTRACTION FROM MOS CIRCUIT DATA
K FUJIYOSHI, M KANEKO, M ONODA
1990 IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS, VOLS 1-4, 4, 3238-3241, 1990
FREQUENCY-DEPENDENT BOUNDEDNESS PROPERTY FOR SWITCHED CAPACITOR NETWORKS
M KANEKO
1990 IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS, VOLS 1-4, 3, 2209-2212, 1990
ALTERNATIVE IMPLEMENTATION OF SYSTOLIC RECURSIVE DIGITAL-FILTERS
M KANEKO
ELECTRONICS LETTERS, 25, 15, 982-983, 1989
Systematic design for switched capacitor networks based on discrete-time state equations
Mineo Kaneko
Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi), 71, 10-21, 1988
A signal‐flow graph representation for switched‐capacitor networks and its application to SC circuit design
Mineo Kaneko, Mahoki Onoda
Electronics and Communications in Japan (Part I: Communications), 70, 2, 35-45, 1987
NEW SIGNAL FLOW REPRESENTATION OF SWITCHED CAPACITOR NETWORKS AND ITS APPLICATION TO THE STRAYS-INSENSITIVE DESIGN.
Mineo Kaneko, Mahoki Onoda
Proceedings - IEEE International Symposium on Circuits and Systems, 531-534, 1985
Z-DOMAIN EXACT DESIGN FOR LDI LEAPFROG SWITCHED-CAPACITOR FILTERS.
Mineo Kaneko, Mahoki Onoda
Proceedings - IEEE International Symposium on Circuits and Systems, 1, 304-307, 1984
Topological formulas for switched capacitor networks
Mineo Kaneko, Hiroaki Kunieda, Mahoki Onoda
Electronics and Communications in Japan (Part I: Communications), 66, 12, 1-9, 1983
Adjoint network approach to sensitivity calculation for switched‐capacitor networks
Hiroaki Kunieda, Mineo Kaneko, Mahoki Onoda
Electronics and Communications in Japan (Part I: Communications), 65, 1, 47-55, 1982