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TANAKA, Kiyofumi Professor, Deputy Dean, Director of Next-Generation Digital Infrastructure Research Area
Information Science, Next-Generation Digital Infrastructure
◆Degrees
B.S., M.S. and Ph.D. from the University of Tokyo (1995, 1997, 2000) The University of Tokyo
◆Professional Experience
2020 - : Japan Advanced Institute of Science and Technology , School of Information Science , Professor
2001 - 2020 : Japan Advanced Institute of Science and Technology , School of Information Science , Associate Professor
2001 - 2005 : Japan Science and Technology Agency, PRESTO Researcher
2000 - 2001 : Research Associate(JSPS) at the University of Tokyo
◆Specialties
Computer systems
◆Research Keywords
プロセッサアーキテクチャ, 並列計算機, リアルタイムシステム, 組込みシステム, 高機能アーキテクチャ
◆Research Interests
Parallel computer architecture
In parallel computer systems, dynamic reduction in messages is an effective scheme for preventing hot-spots which degrade performance. We study how to build a highly functional interconnection network that implements the reduction. Futher, we study adaptive directory scheme for management of shared data.
Memory system for large-scale data
We propose a reconfigurable cache memory that provides a buffer for large-scale data, and DMA mechanisms by a memory controller where stride data sequences are gathered and transferred efficiently. We evaluate the efficiency of them applied to real applications.
Embedded system architecture
We develop the RISC core for embedded systems which is configurable about the hardware elements according to demands on speed, size of hardware and consumption of electricity by various applications. Further, we develop real-time operating system which performs adaptive scheduling. In addition, we investigate reduction in electricity consumption for future architecture.
Processor Architecture for Real-Time Multitasking
A computer is used in multitasking fashion based on time sharing. In this rsearch, we propose the architecture that reduces the time required for switching processor contexts such as register contents and address space when an active task is switched, and alleviates constraints in scheduling of real-time applications.

■Publications

◆Published Papers
Better Scalability: Improvement of Block-Based CNN Accelerator for FPGAs
Yan Chen, Kiyofumi Tanaka
IEEE Access, 12, 187587-187603, 2024
High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs
Yan Chen, Kiyofumi Tanaka
2024 27th Euromicro Conference on Digital System Design (DSD), 503-511, 2024
A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on FPGAs
Yan Chen, Kiyofumi Tanaka
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 183-183, 2024
An Efficient Real-Time Pitch Correction System via Field-Programmable Gate Array
Bowen Tang, Kiyofumi Tanaka
2024 6th International Conference on Image, Video and Signal Processing, 147-154, 2024
Container Auto-scaling System Using Sliding-Window Regression with Fuzzy Entropy
Naoya Yokoyama, Kiyofumi Tanaka
Journal of Information Processing, 32, 916-928, 2024
◆Misc
突発的なWebトラフィックの増減に適応するfuzzy entropyを用いたオートスケーリングシステム
Naoya Yokoyama, Kiyofumi Tanaka
マルチメディア，分散，協調とモバイル シンポジウム論文集(DICOMO 2023), -, 2023
Hardware Implementation of Elliptic Curve Scalar Multiplication Algorithms with Side-Channel Protection
Kiyofumi Tanaka, Atsuko Miyaji
IPSJ SIG Technical Reports, EMB, 2020-EMB-54, 2, 1-8, 2020
FPGA SoCにおける多倍長演算の実装
田中清史
情報処理学会研究報告, EMB, 2019-EMB-53, 42, 1-5, 2020
A Study of Real-Time Extension for RISC-V Processors
Aye Myat Mon, Thiem Van Chu, Kiyofumi Tanaka
IPSJ SIG Technical Reports, EMB, 2019-EMB-51, 7, 1-2, 2019
High-Accuracy and Cost-Effective Neural Networks for Embedded Systems
Jiajun Guo, Amr Ashmawy, Thiem Van Chu, Kiyofumi Tanaka
IPSJ SIG Technical Reports, 2019-EMB-50, 36, 1-8, 2019

■Teaching Experience

Processor Design Laboratory, Enhanced Operating Systems, Operating Systems, Integrated Architecture, Digital Logic and Computer Design, Computer Architecture, Parallel and Distributed Systems Architecture

■Contributions to  Society

◆Academic Society Affiliations
THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, IEEE Computer Society, ACM, INFORMATION PROCESSING SOCIETY OF JAPAN
◆Academic Contribution
Journal Senior Reviewer , Information Processing Society of Japan
Associate Editor of Editorial Committee of Special Issue of Embedded Systems Engineering in IPSJ Journal , Information Processing Society of Japan
Chief Examiner of Special Interest Group on Embedded Systems (SIGEMB) , Information Processing Society of Japan
◆Committee Memberships
・ 情報処理学会 , 組込みシステム研究会運営委員 , 2024-
・ , 科学研究費委員会専門委員 , 2019- 2020

■Academic  Awards

・ 研究会活動貢献賞 , 田中 清史 , 情報処理学会 , 2024
・ 最優秀論文賞 , 横山 尚弥, 田中 清史 , DICOMO 2023 シンポジウム , 2023
・ Outstanding Paper Award , "Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)" , 2021